FPGA-Compatible VESA DSC IP

        DSC is now broadly deployed across video-transport domains. First, in mobile — smartphones and tablets. As display resolution and video quality in mobile devices keep growing, DSC reduces transmission bandwidth, boosts system performance and extends battery life. Second, automotive — cars, and electric vehicles in particular, integrate many cameras and displays; DSC cuts the number of transmission channels, reducing system cost and power. Third, AR/VR and head-mounted displays — DSC lowers transmission latency and improves the visual experience. DSC also serves USB Type-C, TVs and set-top boxes for high-bandwidth applications. Beyond these, DSC fits any scenario that needs to compress video transport bandwidth — for example, in encoder/decoder cards for LED video walls, where a single gigabit Ethernet port can carry a 1080p@60 stream.

         The chart above shows the PSNR of an 8-bit RGB image after DSC compression. The X-axis is compression ratio, the BPP row is post-compression bits-per-pixel, and the MAE row is mean absolute error. Between 1.6× and 3× compression PSNR exceeds 48 dB and image quality is excellent with negligible error — the difference between original and compressed images is virtually imperceptible. At 4× compression PSNR is still 42 dB; distortion at this level is difficult for the human eye to detect, so the compressed image remains visually very close to the original.

         BergLogic's VESA DSC IP is based on the DSC 1.2b specification, written in Verilog as an FPGA IP, and remains backward-compatible with DSC 1.1. During development we used the DSC C-language reference code as the golden simulation model — ensuring identical intermediate data and final output between the two.

         To minimize logic resource usage and lower deployment cost, BergLogic offers DSC IP trimming services. While remaining DSC 1.2b compatible, customers can opt out of optional features (e.g. BP prediction), constrain input image format and bit depth, and so on — reducing FPGA resource usage. For example, restricting input to YUV444 removes the CSC color-space conversion module; restricting bit depth to 8 lets us narrow internal compute widths.

         BergLogic is committed to delivering high-performance video processing IP. Built on our deep video codec expertise and rich FPGA engineering experience, our DSC FPGA IP achieves excellent technical metrics. Key specs follow: