ASIC/SoC Design and Production Services
Encryption IP Core for FPGA
Hardware acceleration of cryptographic algorithms is an important FPGA application area. For deploying crypto workloads, the FPGA approach clearly outperforms CPU/GPU on performance, power, latency and cost. ASIC implementations beat FPGA on raw efficiency but lose on development cycle and cost; FPGA also has the unique advantage of reconfigurability, supporting algorithm switching at runtime — a huge flexibility win.
The figure below compares FPGA, ASIC, GPU and CPU across performance, power, flexibility, cost and development cycle. FPGA strikes a remarkably balanced profile across these dimensions — a "hexagonal warrior", if you will — while the alternatives each have obvious weaknesses (for example, ASIC's long development cycle and rigid flexibility).
BergLogic has been working in the FPGA space for many years and has accumulated extensive experience in improving algorithm performance and reducing resource consumption, with high-quality deliveries across many crypto-acceleration projects. We have built a large library of cryptographic IP cores.
The SHA family of cryptographic hash functions was designed by the U.S. National Security Agency (NSA) and published by the U.S. National Institute of Standards and Technology (NIST). SHA has evolved through SHA-1 → SHA-2 → SHA-3; SHA-1 has been broken, while SHA-2 and SHA-3 — for their strong security and modest compute complexity — see broad use today (Bitcoin famously uses SHA-256 from SHA-2 as its proof-of-work algorithm). BergLogic already offers a range of SHA-2 and SHA-3 IP cores (see table) that can be customized to a customer's performance and interface requirements; given the target spec, we design the optimal pipeline and core count while minimizing resource usage.
| BergLogic SHA-family IPs | Status |
|---|---|
| SHA2-224 | Production |
| SHA2-256 | Production |
| SHA2-384 | Production |
| SHA2-512 | Production |
| Keccak (SHA3) | Production |
The SMx series — the Chinese national commercial cryptographic algorithm standards — is published and certified by China's State Cryptography Administration, with several algorithms now adopted as international standards. The SM family includes SM1/SM2/SM3/SM4/SM7/SM9; the SM1 and SM7 specifications are not publicly disclosed. BergLogic's existing SMx series IP cores are listed below.
| SMx-family IPs | Status |
|---|---|
| SM2 | Production |
| SM3 | Production |
| SM4 | Production |
| SM9 | Production |
Beyond the SHA and SMx families, BergLogic also offers a range of additional encryption / signature algorithm IPs (see table). All of these can be customized at the IP or system level.
| Other algorithm IPs | Status |
|---|---|
| blake | Production |
| bmw | Production |
| groestl | Production |
| jh | Production |
| skein | Production |
| luffa | Production |
| cubehash | Production |
| shavite | Production |
| simd | Production |
| echo | Production |
| hamsi | Production |
| fugue | Production |
| shabal | Production |
| whirlpool | Production |
Beyond module-level and system-level customization of existing crypto IP, BergLogic also offers custom development for other algorithm requirements. Our deep experience in FPGA crypto acceleration ensures high-quality delivery aligned with each customer's needs.