ASIC/SoC Design and Production Services
White Tiger Video Codec Core Boards — White Tiger Z1
White Tiger Z1 is BergLogic's codec core board purpose-built for distributed video deployments. Once the FPGA is loaded with the JPEG2000 codec, the board delivers light-compression distribution capability out of the box. Below is a photo of White Tiger Z1, which integrates all the hardware interfaces required for our video codec and AV over IP solutions.
- In the hardware block diagram:
- • Kintex UltraScale+ FPGA — the core board's main processing chip
- • HDMI 2.0 RX — video input, up to 4K@60fps
- • HDMI 2.0 TX — video output, up to 4K@60fps
- • ETH RGMII0 — Gigabit copper port for transmitting the encoded data stream
- • ETH RGMII1 — Gigabit copper port for transmitting encoded data, hot-standby for ETH RGMII0
- • CPU RGMII — Gigabit copper port connected to the baseboard SoC, providing a network channel to the SoC
- • ETH 10GBASE-R — 10G fiber port for transmitting encoded data; configurable as a Gigabit fiber port
- • BT.656 TX — video output for an unencoded preview stream to the baseboard SoC, where H.264 encoding is performed
- • I²S — audio input / output
- • SPI — FPGA configuration interface, connected to the baseboard SoC
- • UART — FPGA debug interface
The core board connects to the baseboard via an MXM connector. HDMI, I²S, UART, ETH RGMII0/1, ETH 10GBASE-R and similar interfaces pass through the baseboard's corresponding driver chips (HDMI retimer, ETH PHY, etc.) and reach the baseboard front panel directly. CPU RGMII, SPI and BT.656 TX connect to the baseboard SoC (CPU). CPU RGMII is the network link between FPGA and SoC; the SPI interface is the SoC's management channel for configuring FPGA-internal registers.
The White Tiger Z1 core board can serve as either an encoder or a decoder — different FPGA firmware switches the function. The diagrams below show the system block diagram for encoder and decoder firmware respectively.
In the encoder, the HDMI-input video stream is split: one copy goes into the JPEG2000 encoder, another goes through a Scaler module and reaches the baseboard SoC over BT.656 — where it is H.264-encoded to produce a preview stream. The compressed bitstream from the JPEG2000 encoder is wrapped in UDP/IP/MAC into Ethernet packets and dispatched on the network via multicast or unicast. The I²S audio data is similarly packetized into Ethernet frames; video and audio transport are entirely independent and can be routed to different destination IPs. Packetized data flows through an Ethernet-switch module that routes to specific physical ports — the Gigabit copper port or 10G fiber port — as required. The Ethernet switch module also provides the baseboard SoC with its network egress: since the SoC and the FPGA share IP and MAC addresses, all traffic passes through a single front-panel port. On the transmit side, the switch automatically merges SoC network traffic with FPGA-generated video / audio streams; on the receive side, it automatically dispatches packets to the SoC or the FPGA based on packet type, routing video / audio packets to the FPGA and everything else to the SoC.
In the decoder, compressed video data from the network port is de-encapsulated from UDP/IP/MAC and fed into the JPEG2000 decoder. Decoded pixel data enters the VPSS — for crop, scale, layer composition, OSD overlay and similar operations — and is emitted over HDMI TX. VPSS can also accept deep-compression video streams delivered by the SoC over HDMI RX, layering them with JPEG2000-decoded light-compression streams.
Once flashed with FPGA firmware, the White Tiger Z1 core board's FPGA functions like an ASIC — providing complete light-compression distribution capability. We provide a complete, thoroughly validated register set for configuring the FPGA's internal functions; we also provide a reference SoC design (code + detailed documentation), API surface (callable from web and mobile apps), and a web management UI — helping users get familiar with the core board quickly. Customers can integrate the core board's management software with their existing distributed-system control software and keep their original product UX. With our White Tiger Z1 core board and a simple baseboard, a complete light-compression distributed product is straightforward to build. To minimize design effort, we also provide a reference baseboard design — customers can add their own differentiating circuitry on top. The diagram below shows the core board / baseboard interconnect:
Customers can choose appropriate baseboard components to build cost-effective light-compression distributed products, or pick an SoC with H.264 / H.265 capability for deep compression — combining both to build a dual-engine distributed product. Choosing BergLogic's JPEG2000 light-compression core board lets customers rapidly bring distributed video products with strong technical merit and competitive edge to market. For detailed JPEG2000 light-compression specifications, see " FPGA-Based Light-Compression Distributed Video System ".