ASIC/SoC Design and Production Services
Keystone IP Core for FPGA
In projection display and automotive HUD, the keystone distortion caused by misalignment between the device's optical axis and the projection plane has long been a tough industry problem. Conventional optical compensation, constrained by mechanical adjustment range, struggles in complex installation scenarios. BergLogic's Keystone correction IP closes the loop between optical distortion and digital compensation via efficient image preprocessing.
The core idea is an inverse geometric transform: the standard rectangular image is pre-warped into an arbitrary quadrilateral matched to the optical path, which then cancels out the projection system's keystone distortion through spatial-vector neutralization. This "digital-first" correction philosophy ensures the final projected image stays a perfect rectangle regardless of installation angle. The approach applies to ultra-short-throw projection, multi-plane fused HUDs and similar cutting-edge display domains, advancing smart cockpit and immersive A/V experiences to the next level.
Keystone correction result
The Keystone correction is built around two main components: a perspective-transform algorithm and an interpolation algorithm. Based on a homography matrix, the perspective transform builds a 3D-coordinate transformation model. By establishing a bidirectional coordinate mapping between target and source images, it achieves sub-pixel geometric correction accuracy. The algorithm supports dynamic parameter updates — a complete coordinate-system rebuild finishes within 0.5 seconds. For different use cases, two configurable interpolation schemes are offered:
Source-image projection of a single target-image row in the Keystone transform
- • High-efficiency mode: bilinear interpolation over a 2×2 pixel matrix — optimal balance between compute resources and image quality
- • High-quality mode: bicubic interpolation over a 4×4 pixel neighborhood with a cubic convolution kernel — cinema-grade smooth transitions
BergLogic's Keystone IP core uses a fully hardware-accelerated architecture, with the following highlights on FPGA:
- • Pure hardware pipeline — no host software required for parameter calculation or flow control; compatible with processor-less FPGA architectures
- • Extremely simple configuration: just input the four-vertex coordinates of source and target images to start
- • Compact and efficient design — low logic resource footprint
- • Wide deformation range and strong scaling — handles large warps and varying projection distances
- • Fast parameter activation — new configuration takes effect within 0.5 seconds
- • 4 independent deformation regions processed in parallel, each with its own transform parameters — ideal for multi-plane projection scenarios
- • The full pipeline requires only one source-image read/write pass and one deformation-parameter read pass. DDR burst length ≥ 128, data width 256 bits — avoiding frequent read/write switches and cross-row operations for highly efficient memory utilization
Keystone IP key specs:
- • Configuration activation: under 0.5 seconds
- • Processing performance: real-time 4K@60fps
- • Deformation range: a single target-image row can map to up to 1024 source rows
- • Scaling range: 1× to 4× continuously adjustable
- • Processing latency: 1 frame