JPEG2000 Codec IP Core for FPGA

        The BergLogic JPEG2000 codec IP is an RTL (Verilog) FPGA IP that runs on FPGAs from AMD (Xilinx), Altera, Pango and others. The JPEG2000 FPGA IP is delivered in two variants — Standard and Low-Latency. The Standard variant is fully compliant with JPEG2000 Part 1 Amd 1, outputs the standard .jp2 file format and is bit-stream-interoperable with the official JPEG2000 reference software: a .jp2 file produced by BergLogic's JPEG2000 IP can be decoded by the reference software, and vice versa. The Standard variant follows the JPEG2000 specification strictly, achieving PSNR essentially identical to the reference software. The Standard variant handles both still images and video streams. BergLogic's JPEG2000 IP is deeply optimized for engineering deployment — the compact design uses fewer logic resources and consumes less power than competing implementations.

        The Low-Latency variant is optimized for video applications on top of the Standard variant, with the goal of minimizing end-to-end latency. It uses an innovative rate-control algorithm that begins predicting and computing optimal truncation points as soon as a few image lines have been received, achieving much lower latency. The Low-Latency variant outputs a BergLogic-proprietary format, reducing container overhead and enabling faster decode. With the Low-Latency variant, end-to-end JPEG2000 codec latency (HDMI in → JPEG2000 encode → network transport → JPEG2000 decode → HDMI out) is held below 8.5ms, and below 2ms in extreme configurations — well suited to latency-sensitive applications. The progressive transmission property of JPEG2000 is preserved in the IP: the encoder can split a 4K-resolution bitstream into a primary stream and a secondary stream, where the primary carries full 4K information and the secondary carries 1080p; the decoder can choose to decode either the 4K or the 1080p image.

         At low compression ratios BergLogic's JPEG2000 IP shows slightly lower PSNR than the reference software, because the software version uses floating-point arithmetic for higher precision and codes more bit-planes; if more logic resources are allocated, our JPEG2000 IP can match the same PSNR. At higher compression ratios the two versions are virtually identical. To minimize resource usage while serving the typical use case (compression ratio > 10), we adopted a more compact design.

         The JPEG 2000 codec IP runs on the latest FPGA devices, delivering low-latency, high-quality, cost-effective solutions. Combined with BergLogic's other video processing modules (HDMI/SDI I/O, VPSS, network transport, etc.), it enables distributed video systems and similar applications. This JPEG2000 FPGA IP has been fully validated and deployed at scale on Xilinx Kintex-7 and UltraScale/UltraScale+ families, reaching stable commercial status. BergLogic also offers a hardware platform (based on Xilinx KU3P FPGA) to demonstrate JPEG2000 encode/decode and observe bitrate, image quality and latency parameters in practice. For specialized resolutions, frame rates and bit depths, BergLogic offers custom development services to produce minimum-resource variants and lower JPEG2000 deployment cost.

JPEG2000 codec demo environment

	Standard	Low-Latency
Max performance	4K@60fps	4K@60fps
Latency (end-to-end)	1 frame + 2ms	8.5ms
Color space	RGB / YUV444 / YUV422 / Grayscale (PGM)	RGB / YUV444 / YUV422
Bit depth	8 / 10 / 12	8 / 10 / 12
Wavelet (DWT) type	9/7 wavelet (lossy), 5/3 wavelet (lossless)	9/7 wavelet (lossy)
Wavelet (DWT) levels	3 to 6	3 to 6
Quantization step	Configurable	Configurable
Quality layers	1	1
Compression ratio	1× to 25×, dynamically configurable	1× to 25×, dynamically configurable
Encoder input format	AXI-Stream	AXI-Stream
Encoder output format	.jp2, .j2c	BergLogic proprietary format
Decoder input format	.jp2, .j2c	BergLogic proprietary format
Decoder output format	AXI-Stream	AXI-Stream
Codeblock (CB) size	32×32, 64×64	64×4, 16×16, 32×8
Progression order	CPRL	PCRL