ASIC/SoC Design and Production Services
JPEG XS Codec IP Core for FPGA
BergLogic JPEG XS IP Core is fully compliant with ISO/IEC 21122-1 — a lightweight codec designed for ultra-low-latency, visually lossless compression. It aligns perfectly with SMPTE ST 2110-22, IPMX and other professional video standards, making it an ideal choice for video over IP in broadcast and ProAV.
As an interoperable low-latency mezzanine codec, JPEG XS delivers visually lossless image compression for audio/video markets at resolutions from HD up to 8K and beyond — meeting the requirements of broadcast, professional video, VR/AR, sensor compression and many other applications.
Industry Context & Market Needs
The video industry is shaped by two major trends. First, resolutions continue climbing toward 4K and 8K, and HDR adoption is driving explosive growth in data volume and bandwidth. Second, the industry is gradually moving away from SDI and other proprietary cabling toward standard Ethernet-based IT infrastructure.
In this context, lightweight compression has become a focal point. The ideal scheme must let users scale resolution, frame rate and stream count while retaining the advantages of uncompressed video — high interoperability, visually lossless quality, low power, ultra-low codec latency, simple implementation and small silicon footprint. JPEG XS is the international standard born of these demands, and has been adopted by SMPTE ST 2110-22 as a compressed video stream format.
Core Advantages
Ultra-Low Latency
Sub-millisecond fixed latency; end-to-end strictly below 32 lines — supports real-time interaction, remote production and similar demanding applications.
Visually Lossless
Original image detail preserved at 6×-10× compression; quality remains intact across multiple encode/decode iterations.
Minimal Resource Footprint
No external DDR required; runs on mid-range FPGAs with extremely low logic and Block RAM usage — reducing system cost.
Standards Compliant
Fully compatible with SMPTE ST 2110-22, IPMX, ISO/IEC 21122-1 and related international standards — guaranteeing interoperability.
Constant Bitrate
CBR and VBR rate control; integrates seamlessly with ST 2110 for stable AV over IP transport.
Generation Stability
No quality degradation across multiple encode/decode iterations — ensures quality consistency through multi-stage processing.
Applications
Broadcast & Production
SMPTE ST 2110 IP gateways, remote production switchers, video contribution links, 4K/8K UHD multi-channel recording.
JPEG-XS-based end-to-end 4K/8K IP production has been deployed at scale.
Professional AV over IP
IPMX distributed matrices, KVM extenders, digital signage, conferencing systems, campus broadcasting.
SMPTE ST 2110-22 compliant; constant-bitrate transport.
Real-Time Video Storage
In-camera storage (SSD/SD), video recording devices, slow-motion replay systems.
No quality loss across multiple codec passes; 3×-5× storage efficiency improvement.
VR / AR Applications
Head-mounted displays, VR gaming, immersive exhibitions, remote collaboration.
8M+ pixels, 90fps+; ultra-low latency keeps motion and display in sync.
Industrial & Medical
Endoscope video, machine vision, industrial inspection, automotive sensor compression.
Ultra-low latency, low power; supports direct Bayer-pattern sensor connections.
BergLogic JPEG XS IP Advantages
- Deeply Optimized, Resource Efficient: Our JPEG XS implementation is deeply tuned for FPGA — fewer logic resources while running at higher clock frequencies, saving 30%+ logic compared to competing solutions.
- Commercial Quality, Stable & Reliable: The IP has gone through thorough RTL verification, FPGA prototyping and system-level testing — reaching commercial-grade quality, with a complete demo environment and reference design.
- Local Service, Fast Response: A dedicated local technical team provides efficient support and customization with zero time-zone friction — quick response to customer needs.
- Strong Customization: Custom IP for specific FPGA models and target specs (resolution, frame rate, bit depth, interface), with support for Chinese-domestic FPGA platforms (Fudan Micro, Anlogic, Pango etc.).
- Complete Delivery Package: Synthesized netlist, complete simulation environment, test vectors, detailed user guide and reference design — accelerating customer time-to-market.
| Video Format |
Color spaces: RGB, YCbCr, YUV444, YUV422 Chroma sampling: 4:4:4, 4:2:2, 4:2:0, 4:0:0 (Alpha channel supported) Bit depth: 8 / 10 / 12-bit (14 / 16-bit available as a customization) Resolution: Arbitrary resolutions up to 8K / 10K+, HDR (PQ / HLG) supported |
|---|---|
| Codec Performance |
Compression standard: ISO/IEC 21122-1 encoder / decoder Compression ratio: 1× to 10× dynamically adjustable, visually lossless Latency: < 1ms (fixed sub-millisecond, below 32 lines) Rate control: CBR and VBR with precise bitrate control |
| Hardware Implementation |
Target FPGAs: AMD Xilinx (Artix-7, Kintex-7, Ultrascale/+, Versal etc.) / Intel Altera (Cyclone V/10, Arria 10, Stratix V/10, Agilex etc.) Resource usage: Extremely low logic and Block RAM consumption, no external DDR required; custom support for Chinese-domestic FPGA platforms. |
| Configuration Support |
Wavelet levels: Vertical ≤ 2, Horizontal ≤ 5 Complexity profiles: Light_subline, Light, Main, High (full support) File format: .jxs |
| Algorithm |
Step 1 — Decorrelation transform: Discrete Wavelet Transform (DWT) for energy compaction, reducing image data redundancy Step 2 — Rate control: Fine-grained rate control algorithm dynamically adjusts quantization to hit the target bitrate precisely Step 3 — Entropy coding: Entropy-codes the highest bit-plane of each coding group, with specialized handling for all-zero significance groups to further improve efficiency |
| Operating Modes |
Light_subline Profile: Lowest complexity — for resource-constrained scenarios Light Profile: Low complexity — balances compression efficiency and resource usage Main Profile: Medium complexity — better compression quality High Profile: High complexity — best compression quality |