In-house cores, system optimization
Codec, media transport, timing and control modules can be adapted together, enabling coordinated design of datapaths, buffers and end-to-end timing.
IPMX FPGA Solution
IPMX is an open standards framework for professional AV, enabling interoperability between devices from different manufacturers.
BergLogic IPMX FPGA solutions combine in-house video codec IP and media transport technology, with delivery options from core IP and combined subsystems to hardware platforms and supporting software. Integrate into existing equipment or develop a new product with coordinated JPEG XS, ST 2110, NMOS and timing across the FPGA, hardware interfaces and application software. Performance, resource use and features are tailored to meet IPMX requirements for the selected configuration.
From in-house cores to a complete IPMX product
Reusable platforms, efficient development
Core IP, building blocks, reference projects and supporting software reduce repeated work, focusing engineering on customer features, integration and product validation.
Delivery that fits your architecture
Start with individual IP, a combined subsystem or a hardware platform solution. Select an integration path around your existing equipment and product plans, with project-specific deliverables.
One integration team, room to customize
One team coordinates FPGA, hardware interfaces and application software, resolving cross-module issues and supporting agreed feature, branding and workflow customization.
CLD-4K60: complete IPMX product solution
CLD-4K60 is a complete IPMX product solution for 4K60-class JPEG XS applications, comprising the CLD-4K60-TX sender and CLD-4K60-RX receiver. Each integrates JPEG XS, ST 2110, NMOS, timing and device control on a single FPGA SoC.
CLD-4K60-TXHDMI input · JPEG XS encoding · IPMX sending
CLD-4K60-RXIPMX receiving · JPEG XS decoding · HDMI output
The platform is intended for evaluation, product development and customer-branded products. Application software can be tailored for branding, interface styling and workflows; FPGA features, hardware interfaces, memory and control configurations are assessed for the target platform and project.
CLD-4K60-TX/RX is planned for formal release in early 2027 for evaluation, development and commercial product delivery. Evaluation arrangements and delivery configurations are agreed per project. Images show enclosure concepts.
Standard modules that fit your product architecture
JPEG XS, ST 2110, NMOS and timing modules can connect to your existing media interfaces, control software and product features. Use them individually or in combination; the complete system is coordinated to meet IPMX requirements for the selected configuration.
| Core component | Capability |
|---|---|
| JPEG XS codec | Low-latency image compression and decompression between pixel streams and compressed bitstreams |
| ST 2110 media transport | Packetization, sending, receiving, buffering and recovery for JPEG XS video and PCM audio |
| Timing and media clocks | Time references, media clock recovery and output timing coordination |
| NMOS and system software | Device discovery, capability description, connection management and runtime configuration |
Profile and performance options
| Configuration | Available options |
|---|---|
| JPEG XS versions | High and High/TDC-compatible versions are available to suit application requirements. |
| Processing capability | Configurations support FHD (1920×1080) and UHD at 4K60 or 4K120. |
| Performance customization | Processing throughput, parallelism and resource allocation can be tailored to the target resolution, frame rate and FPGA/SoC platform. |
Profile, resolution and frame-rate combinations depend on the selected IP, platform, interfaces and network bandwidth. These are module-level options, not specifications for the CLD-4K60 hardware product.
Explore JPEG XS FPGA IP · ST 2110 IP Suite for JPEG XS
Design the product around IPMX system requirements
BergLogic translates IPMX media, synchronization, output and control requirements into coordinated FPGA datapaths, board clocks, MAC interfaces and application software, turning core modules into a complete system for the customer's equipment.
Sender
HDMI input adaptationJPEG XS encodingST 2110 sendingEthernet MAC/PHY
Receiver
Ethernet MAC/PHYST 2110 receivingJPEG XS decodingOutput buffering / HDMI adaptation
Timing and hardware
ST 2059/PTP · MAC timestamp insertion and capture · Board clocks · Media clock recovery · HDMI RX/TX frame-rate adjustment · Network and memory interfaces
Control and software
NMOS · SDP · Drivers · Initialization and configuration · Status and error handling · Customer application interfaces
The FPGA handles JPEG XS encoding and decoding, media packets, traffic shaping, receive buffers and real-time scheduling; the processor manages the device and runtime control. PCM audio is carried through its associated media path.
- Output buffers and playout: Plan buffer capacity, memory scheduling and recovery around network arrival characteristics, decoder pipelines and display output cadence.
- HDMI frame-rate adjustment: Coordinate media clock recovery, frame-rate adjustment and continuous output for the input/output clock architecture and synchronous or asynchronous operating mode.
- ST 2059/PTP and MAC timestamps: Implement standards-based timing with timestamp insertion and capture on the target MAC, integrating board clock control and interface behavior.
FPGA engineering and system optimization
Development efficiency: Reuse in-house IP, building blocks and reference projects, then combine, tailor and extend them for the product. Coordinated interfaces, clocks, drivers and verification reduce repeated development and integration rework.
Resource efficiency: Optimize datapaths, parallelism, pipelines, buffering and memory access around the target device, throughput and latency. Reduce duplicate logic and unnecessary data movement to leave room for customer features.
Applications
HDMI over IP AV senders and receivers.
Professional displays and AV distribution equipment.
Endpoints for meeting rooms, education and presentation systems.
Video walls and custom FPGA/SoC AV over IP products.
System functions for real AV devices
| System capability | Functions |
|---|---|
| Video and audio | JPEG XS video, PCM audio and HDMI input/output, configured for the media format, bitrate and network bandwidth |
| Discovery and connection | NMOS discovery, registration and Sender/Receiver connection management, keeping configuration aligned with actual media flows |
| Format and display adaptation | Coordinate media formats, EDID, HPD and HDMI behavior with device capabilities and display requirements |
| Timing and output | Configure synchronous or asynchronous operation for the deployment, coordinating media clocks, receive buffers and output cadence |
| Monitoring and recovery | Expose connection, media, timing, buffer and error status; handle input changes, stream interruption and recovery |
Add scaling, window composition, OSD, your own control interface and application features to differentiate your product.
From individual IP to a complete system
| Adoption path | Deliverables and customer work |
|---|---|
| Individual IP | BergLogic provides: Selected cores, interface documentation and agreed verification material Your remaining work: Product architecture, platform adaptation and system integration |
| Combined subsystem | BergLogic provides: Integration project, drivers and control interfaces for the agreed modules Your remaining work: Connect your hardware, interfaces and application features |
| Hardware platform / complete product solution | BergLogic provides: Hardware, firmware and supporting software under the release plan and project agreement Your remaining work: Product customization and system validation for the chosen approach |
Deliverables
- IP delivery format, system interconnections, reference projects and verification material are agreed for the selected configuration.
- Firmware, drivers, NMOS components, API/control interface documentation and reference applications follow the project scope.
- Interface, integration and runtime documentation are included as agreed; project editability, design material and third-party component licensing are defined for the product and engagement.
Platform adaptation and integration
- Adapt FPGA/SoC, video and network interfaces, MAC timestamps, board clocks and memory access.
- Tailor configurations, extend features and debug the combined system against throughput, latency and resource targets.
- Customize application software, branding and workflows. FPGA feature changes and hardware interface changes are assessed separately.
Common integration questions
Can we start with IP, a subsystem or a hardware platform?
Yes. Integrate selected cores into an existing product, connect a combined subsystem to your hardware, or plan a new product around CLD-4K60. The adoption path, platform status and delivery scope are discussed for your project.
Can the solution be adapted to our FPGA and hardware?
We assess throughput, resources, memory, interfaces and clocks on the target platform, then agree the FPGA features, board adaptation and software integration scope. Hardware interface changes and application software customization are assessed separately.
How does the complete solution differ from the ST 2110 IP Suite?
The ST 2110 IP Suite provides media transport, drivers and SDP tools. The complete solution adds JPEG XS, NMOS, output buffering, HDMI frame-rate adjustment and timing, with product-level system design for the customer's equipment.
What is the CLD-4K60 release plan and how can we adopt it?
CLD-4K60-TX/RX is planned for formal release in early 2027 for evaluation, product development and commercial product delivery, with agreed branding and application software customization. Evaluation, availability and delivery configurations are confirmed per project.
Plan the IPMX integration path for your product
Share your application, media formats, interfaces, FPGA/hardware platform, and throughput, latency and resource targets. BergLogic can assess an IP, subsystem or hardware-platform approach and agree the customization, delivery and validation scope.
Discuss Your Integration